Michael Caisse wrote:
Phil Endecott wrote:
And while thinking about hardware description languages, note also that they don't expose any sort of dataflow model even though the underlying circuit often has that sort of structure.
I don't think I understand. Verilog supports dataflow modeling and for anything non-trivial is the main mode of modeling. What am I missing?
In Verilog (or VHDL), if I have two components that I want to "pipe" together I need to declare a wire that will be the channel for the communication and then declare the two components with this wire connected to the appropriate port. Something like this: wire[7:0] a; ExampleSource src (.the_output(a)); ExampleSink sink (.the_input(a)); As far as I am aware, neither language has syntax to pipe them together more concisely, i.e. ExampleSource src >>= ExampleSink sink;
I think questioning a library's audience and usefulness is a requirement but I am surprised at the number of people who don't see how/why dynamic dataflow is useful. Are you questioning the value of dataflow modeling or this specific library?
I am questioning it all, but with an open mind ready to be convinced of its value.
I use a dataflow framework that is driven from XML description files. The framework utilizes dynamically loaded components as Stjepan has described in an earlier post. The framework has been deployed in applications ranging from digital video/audio systems to aviation flight/meteorology equipment in international airports.
I hope to have an opportunity to review the Dataflow library.
Please do! As soon as some people who actually know something about Dataflow start posting comments then I will shut up. My comments are intended really just to provoke debate. Regards, Phil.