"Helge Bahmann" <hcb@chaoticmind.net> wrote in message news:alpine.DEB.1.10.0912111612520.13830@m65s28.vlinux.de...
On Fri, 11 Dec 2009, Andy Venikov wrote:
Helge Bahmann wrote:
This is however NOT possible because you are not allowed to make any memory access between ll and sc -- some CPUs (definitely older mips, but not ppc, unsure about many of the other architectures) clear the reservation on _any_ memory reference and will cause this sequence to always fail. Alpha has the fun requirement of a memory barrier before you are allowed to dereference "tmp", which just provides another way to kill your reservation. PPC as well. 7447, for example, will invalidate the "reservation bit" after writing to ANY memory location.
Cool, this makes the whole thing model-specific behavior and thus even more fun :) On the ppc 7455 available to me it not only works, but the "stwcx." in fact behaves more like a CAS (it remembers the value loaded by lwarx, and succeeds if it matches -- thus ABA detection won't work for entirely different reasons).
Other fun restrictions that I remember from some architecture manual (I don't know which, think it was also some mips flavor): No taken branch allowed between ll/sc.
The message should however be clear: ll/sc is *brittle* and not usable for ABA prevention.
FWIW, it's all in `Book II: PowerPC Virtual Environment Architecture' Appendix `B' which you can get here: http://www.ibm.com/developerworks/systems/library/es-archguide-v2.html Especially section `B.3 List Insertion'. You have got to take extreme care when implementing this on a PPC. You don't want something like false-sharing to break reservations. You have to make sure to align everything on cache line boundaries _and_ to ensure proper padding between non-related elements, assuming that reservation granule is a cache line. All of that good stuff! ;^)