Matt Hurd wrote: [...]
But why is a concurrent-aware setter useful if its effects aren't visible to the other threads?
In what way do you mean they not visible?
Such aligned memory operations are guaranteed to be atomic on ia32 at a system wide level AFAIK.
On IA32, sure, but not on other architectures.
Yup. Which gets back to the subject line...
On IA32, - stores have release semantics (sink-load/store mbar for preceding loads/stores in the program order); - loads have acquire semantics (hoist-load/store mbar for subsequent loads/stores in the program order); - lock instructions have compound release and acquire semantics (fully fenced). See Plan9 story for an illustration of lockless stuff that needs store-load fence (compound sink-store and hoist-load mbar) on IA32. http://groups.google.com/groups?selm=414E9E40.A66D4F48%40web.de (Subject: std::msync) regards, alexander.