Marshall Clow wrote:
"Do not use the PowerPC instructions Load Reserved (lwarx) and Store Conditional (stwcx) to implement atomicity in your preemptively threaded application. As described in DTS Technote 1137 Disabling Interrupts on the Traditional Mac OS, these instructions are non-portable and are tricky to use correctly across the full spectrum of PowerPC implementations."
A couple of posters have referred to this as "smells-like-FUD", and "fails to state any technical reasons". To me, that sounds like denial.
The recommendation above is correct. The instructions are obviously non-portable and are, indeed, tricky to use correctly.
Apple has committed to provide routines that work on all PPC CPU that they ship. Why in the world would you choose not to use them, if they do what you need?
Because their memory synchronization properties are not documented. They _probably_ are fully fenced. But it's not guaranteed. Even if it were guaranteed, we don't need a full fence.
If I was writing this code, I would not want to take on the burden of research, testing, and ongoing maintenance that this implies. Certainly "It works fine on my machine" is not sufficient, given these warnings. Off the top of my head, I would want to test against the 601, 603, 603e, 604, G3 (several revisions), G4 (several revisions) and G5.
CPUs do happen to have bugs. But this isn't very common, and the existing CPU bugs are usually well-known. "Programmers equate an atomic update with a full fence" is a much better explanation of Apple's warnings... on the basis of the available information. They _could_ have identified a system where lwarx/stwcx. do not work reliably, after all.