Cory Nelson schrieb:
On 10/10/07, Markus Schöpflin <markus.schoepflin@web.de> wrote:
Ion Gaztañaga schrieb:
Markus Schöpflin escribió:
Hello,
this may be a silly question, but I have been wondering what the atomic read and write primitives are actually supposed to do?
I mean, from the readers or writers POV a read or write is always atomic, isn't it? Am I missing something very obvious here? In some architectures, a 32 read might not be atomic (even if the read is aligned). I think that Intel system is always atomic. They are there for completeness, to support systems where read or write might not be atomic. Sorry for being dense, but what exactly do you mean when you say a read might not be atomic? Are you thinking of memory barriers here? Or is it something else? Is there somewhere a definition of what atomic exactly means here?
I believe he is referring to cache coherency - on x86 and x64, read and write are always atomic in the sense that a read will never see half of the old value and half of a write.
So it's not an issue of memory barriers, but of a hardware not being able to serialize concurrent r/w access to the same location (either register or memory address)? Markus