Howard Hinnant wrote:
My real problem is that I'm a neophyte in the bewildering world of gcc asm syntax.
Aren't we all?
I've been studying:
http://gcc.gnu.org/onlinedocs/gcc-4.0.3/gcc/Extended- Asm.html#Extended-Asm
on the good advice of some colleagues. The other advice I'm getting is that there is still a bug in:
boost/detail/sp_counted_base_gcc_ppc.hpp
Looking at just atomic_increment:
inline void atomic_increment( int * pw ) { int tmp;
__asm__ ( "0:\n\t" "lwarx %1, 0, %2\n\t" "addi %1, %1, 1\n\t" "stwcx. %1, 0, %2\n\t" "bne- 0b":
"=m"( *pw ), "=&b"( tmp ): "r"( pw ): "cc" ); }
My current understanding is that the "=m" constraint indicates that *pw is write-only, and should be changed to "+m" to indicate read/ write (to memory). Indeed when I make this change, my test case clears right up. It also appears that atomic_decrement and atomic_conditional_increment could use this treatment as well.
Looks like a bug. Hmm. I think I remember something about +m causing internal compiler errors and not working in general (for some versions of g++); that's why the x86 version uses "=m"(*pw) as an output and "m"(*pw) as an input. But there are no "m"(*pw) inputs in PPC and IA64! Can you try the +m change on as many g++ versions as possible? I may be misremembering things. Or can you try the potentially safer alternative of adding "m"( *pw ) as an input and see whether this also works? If you contribute your test case, this will be appreciated, too.