On 05-04-18 06:58, Ggh via Boost wrote:
Seth!! THANK YOU!!!THANK YOU!!!
:)
Greg Cheers. I don't mean to rain on your parade, but perhaps I forgot to stress how... futile this still is.
For one thing, the complete same thing can be achieved with a relatively straightforward standard makefile, just replacing `OBJS` with a pattern substitution over a wildcard() call, and replacing all those "fixed" rules with some pattern rules like: %.o:%.c $(CC) $(CFLAGS) -c $< -o $@ %o:%.cpp $(CXX) $(CXXFLAGS) -c $< -o $@ -include $(OBJS:%.o=%.d) In fact as written, the rules for %.o are redundant as they match the builtin defaults (at least for GNU Make), as you can find out by using make -p. As an example, here's a simple FIXED `Makefile` that basically reproduces all the things you had in your C++ program, but without any external code: https://gist.github.com/sehe/2720161cec8452c38a5eb5808a7dd919 It can build all the targets from one file, regardless of how many files there are. In fact it's better in some respects (this makefile correctly deals with e.g. having `a.cpp`, `a.cxx` and `a.c` all in the same directory). Example runs to bootstrap the same program again, this time using **just** the one Makefile: https://i.imgur.com/boBdfID.png Now, look at how CMake already works with ninja, Make and MSBuild. I don't really think you are ready going to improve things yet. Of course, you can generate your own makefiles for your own convenience, though I'd probably write it in Python, Perl or something like that. Regards, Seth