24 Oct
2006
24 Oct
'06
2:07 p.m.
Anthony Williams wrote:
"Peter Dimov" <pdimov@mmltd.net> writes:
Chris Thomasson wrote:
Here is the initial experimental pseudo-code that I am thinking about prototyping in IA-32 Assembly:
http://groups.google.com/group/comp.programming.threads/browse_frm/thread/5f...
Seems like it can work. Don't you only need one bit for writes though?
It's essentially the same algorithm I've used in my latest offering on the thread_rewrite branch.
Do you plan to document the algorithm? I'm interested in the following scenario: - K active readers are holding the lock - a writer is waiting for the above - L readers are wating for the writer Since you seem to only store K+L (Chris's algorithm has separate counts), how do you know when to signal the writer?