< Forward Quoted > Newsgroups: comp.arch Subject: Re: lwarx/stwcx on PowerPC 970 References: <4257CC7A.252E5B2@web.de> Message-ID: <opsoyu88daqm36vk@grunion> Date: Sat, 09 Apr 2005 09:18:34 -0400 From: "Joe Seigh" <jseigh_01@xemaps.com> Joe Seigh wrote:
On Sat, 09 Apr 2005 14:37:14 +0200, Alexander Terekhov <terekhov@web.de> wrote:
http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/3A2D397F9A3202BD87...
Says that "Every larx executed should have an accompanying stcx to clear the reservation." and that "Additional information regarding Larx/Stcx instructions and usage can be found in the "PowerPC Microprocessor Family: Programming Environments Manual for 64 and 32-Bit Microprocessors".
"Additinal information" shows coding examples like this:
<quote>
loop: lwarx r6,0,r3 #load and reserve cmpw r4,r6 #first 2 operands equal ? bne- exit #skip if not stwcx. r5,0,r3 #store new value if still reserved bne- loop #loop if lost reservation exit: mr r4,r6 #return value from memory
</quote>
So, who's right here?
Just "strongly recommended", not required. The reservations obviously aren't recursively counted since the OS has no way of knowing the count in order to "clear" the reservations. Unless there's some performance hit for maintaining the reservation, I can't see any reason to worry about it.
-- Joe Seigh
< /Forward Quoted > On any sensible Power {PC} implementation (especially MP), redundant stwcx will negatively affect performance, not the other way around. regards, alexander.