Markus Schöpflin escribió:
So it's not an issue of memory barriers, but of a hardware not being able to serialize concurrent r/w access to the same location (either register or memory address)?
Yes. With 32 bits there is no problem for current architectures, but imagine we have a library for atomic 64 bit integers. Raw read and write would not be atomic in 32 architectures because memory read/write would be implemented with two memory accesses. We must also make sure that cache and other issues maintain the atomicity. I'm not an atomic operation expert (even not a beginner). Functions were inspired by apache portable runtime atomics, and there atomic read and writes were wrapped. I just followed the example because I know that 32bit operations were atomic in Intel32 but I also know that there are systems (surely as used as Intel) that have not this property.
Markus
Regards, Ion