On Fri, May 21, 2010 at 11:14 AM, Simonson, Lucanus J <lucanus.j.simonson@intel.com> wrote:
I have just added a tutorial to the documentation. The tutorial walks the reader through the requirements, design and implementation of a toy layout versus schematic comparision application. I would like feedback from the community on whether this is what you are looking for in a tutorial. Also I'd like to check with my review manager, Fernando, if this tutorial satisfies the acceptance requirement that I add a tutorial to the documentation. The tutorial can be found here: https://svn.boost.org/svn/boost/sandbox/gtl/doc/gtl_tutorial.htm
At this stage I think I have satisfied the acceptance requirements from the review and would like to coordinate merging the library onto the trunk and release branch to get into the next release of boost. A little guidance from the release manager would be appreciated.
I just took a look at this having some interest in using the polygon library as a user. Please take these first impressions with a grain of salt because I didn't participate in the review. That said here's some of my thoughts (unfiltered): * You use quite a lot of jargon that's specific to the chip design field. I'm not sure if normal C++ developers are your target audience, but a tutorial on how to do VLSI layout might not be the best. If you still really want to use that domain, then you might as well explain a few things before you start diving into the rationale of why you'd want to check your chip layouts using a program. * I understand that there are already industry standards when it comes to chip layout and other things, however I find just the normal problems with polygons solved easily would be a huge and powerful tutorial. Things like what the minimum dimensions should be for a set of smaller polygons to be contained in a single rectangle (minimization problem, maybe for the garment industry) or the maximum number of triangles of a given dimension can be fit in a given polygon (maximization problem, maybe for the construction industry). Naive question: does it have to be specific to VLSI chip design or did it just come out in the review? * Given that I don't see where this tutorial fits in the whole scheme of documentation, this tutorial seems to rely on a lot of missing context. Is that intentional by virtue of placement, or is this supposed to be a stand-alone tutorial? I haven't really dug into the details of the tutorial and I'll trust the experts when it comes to the details of the solution. However, I think it would be powerful to show how the library can be used for "normal" everyday and considerably non-trivial problems that are made trivial by the library. Thanks and I hope this helps! -- Dean Michael Berris deanberris.com