"Andy Venikov" <avenikov@gmail.com> wrote in message news:hfrs5q$anq$1@ger.gmane.org...
Helge Bahmann wrote:
There are valid uses for CAS with and without various types of barriers. See the explicit memory_order specification in my atomic operations library.
So, CAS by itself doesn't imply anything, it's all about how you call it, right?
Humm, kind of. CAS on certain architectures actually implies quite a bit (e.g., `LOCK' prefix on x86-32/64). However, since this is on a Boost Forum I should probably be thinking abstract, in the sense of creating highly portable algorithms in order to help make portions of the Boost libraries expansive programming experience easier, so to speak; right? ;^) Therefore, CAS is an atomic RMW with absolutely no effect on memory visibility. However, I think that the return value from failed CAS to an address A can be thought of as a "load". On the flip side, a successful CAS on address B is basically a "store" in the sense of the successful RMW portion of the CAS itself. The "load" from A can rise above the "store" to B. CAS is irrelevant here and an external memory barrier operation might need to be executed after the store to B in order to ensure that it is "fully rendered into visible memory" _before_ the load from A is "committed".