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[Context] RFR: Add support for ARM aarch64 architecture
by Edward Nevill 25 Feb '15

25 Feb '15

Hi, I hope this is the right place to post this. The following patch adds support for ARMs aarch64 architecture on Linux (there is existing iOS support for aarch64). I have run the context regression test on this on an aarch64 board running Ubuntu 14.04 with gcc 4.9.1 and it passes all OK. Could someone please review this patch and if OK push it? Many thanks, Ed. --- CUT HERE --- commit bd34672217ff3bcee185f9c7383179342ec2fe9b Author: Edward Nevill <edward.nevill(a)linaro.org> Date: Mon Feb 23 14:37:45 2015 +0000 Add support for ARM aarch64 architecture diff --git a/build/Jamfile.v2 b/build/Jamfile.v2 index 80d1c46..edd4400 100644 --- a/build/Jamfile.v2 +++ b/build/Jamfile.v2 @@ -253,6 +253,14 @@ alias asm_context_sources <toolset>darwin ; +alias asm_context_sources + : [ make asm/make_arm64_elf_gas.o : asm/make_arm64_elf_gas.S : @gas ] + [ make asm/jump_arm64_elf_gas.o : asm/jump_arm64_elf_gas.S : @gas ] + : <address-model>64 + <architecture>arm + <binary-format>elf + ; + # MIPS # MIPS/O32/ELF alias asm_context_sources diff --git a/config/arm.cpp b/config/arm.cpp index 6a83737..6eece0b 100644 --- a/config/arm.cpp +++ b/config/arm.cpp @@ -6,7 +6,7 @@ // accompanying file LICENSE_1_0.txt or copy at // http://www.boost.org/LICENSE_1_0.txt) -#if !defined(__arm__) && !defined(__thumb__) && \ +#if !defined(__aarch64__) && !defined(__arm__) && !defined(__thumb__) && \ !defined(__TARGET_ARCH_ARM) && !defined(__TARGET_ARCH_THUMB) && \ !defined(_ARM) && !defined(_M_ARM) #error "Not ARM" diff --git a/src/asm/jump_arm64_elf_gas.S b/src/asm/jump_arm64_elf_gas.S new file mode 100644 index 0000000..3e0e2c2 --- /dev/null +++ b/src/asm/jump_arm64_elf_gas.S @@ -0,0 +1,128 @@ +/******************************************************* + * * + * ------------------------------------------------- * + * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | * + * ------------------------------------------------- * + * | 0x0 | 0x4 | 0x8 | 0xc | 0x10| 0x14| 0x18| 0x1c| * + * ------------------------------------------------- * + * | d8 | d9 | d10 | d11 | * + * ------------------------------------------------- * + * ------------------------------------------------- * + * | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | * + * ------------------------------------------------- * + * | 0x20| 0x24| 0x28| 0x2c| 0x30| 0x34| 0x38| 0x3c| * + * ------------------------------------------------- * + * | d12 | d13 | d14 | d15 | * + * ------------------------------------------------- * + * ------------------------------------------------- * + * | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | * + * ------------------------------------------------- * + * | 0x40| 0x44| 0x48| 0x4c| 0x50| 0x54| 0x58| 0x5c| * + * ------------------------------------------------- * + * | x19 | x20 | x21 | x22 | * + * ------------------------------------------------- * + * ------------------------------------------------- * + * | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | * + * ------------------------------------------------- * + * | 0x60| 0x64| 0x68| 0x6c| 0x70| 0x74| 0x78| 0x7c| * + * ------------------------------------------------- * + * | x23 | x24 | x25 | x26 | * + * ------------------------------------------------- * + * ------------------------------------------------- * + * | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | * + * ------------------------------------------------- * + * | 0x80| 0x84| 0x88| 0x8c| 0x90| 0x94| 0x98| 0x9c| * + * ------------------------------------------------- * + * | x27 | x28 | FP | LR | * + * ------------------------------------------------- * + * ------------------------------------------------- * + * | 40 | 41 | 42 | 43 | | | * + * ------------------------------------------------- * + * | 0xa0| 0xa4| 0xa8| 0xac| | | * + * ------------------------------------------------- * + * | PC | align | | | * + * ------------------------------------------------- * + * * + *******************************************************/ + + .cpu generic+fp+simd + .text + .align 2 + .global jump_fcontext + .type jump_fcontext, %function +jump_fcontext: + # prepare stack for GP + FPU + sub sp, sp, #0xb0 + +# Because gcc may save integer registers in fp registers across a +# function call we cannot skip saving the fp registers. +# +# Do not reinstate this test unless you fully understand what you +# are doing. +# +# # test if fpu env should be preserved +# cmp w3, #0 +# b.eq 1f + + # save d8 - d15 + stp d8, d9, [sp, #0x00] + stp d10, d11, [sp, #0x10] + stp d12, d13, [sp, #0x20] + stp d14, d15, [sp, #0x30] + +1: + + # save x19-x30 + stp x19, x20, [sp, #0x40] + stp x21, x22, [sp, #0x50] + stp x23, x24, [sp, #0x60] + stp x25, x26, [sp, #0x70] + stp x27, x28, [sp, #0x80] + stp x29, x30, [sp, #0x90] + + # save LR as PC + str x30, [sp, #0xa0] + + # store RSP (pointing to context-data) in first argument (x0). + # STR cannot have sp as a target register + mov x4, sp + str x4, [x0] + + # restore RSP (pointing to context-data) from A2 (x1) + mov sp, x1 + +# # test if fpu env should be preserved +# cmp w3, #0 +# b.eq 2f + + # load d8 - d15 + ldp d8, d9, [x0, #0x00] + ldp d10, d11, [x0, #0x10] + ldp d12, d13, [x0, #0x20] + ldp d14, d15, [x0, #0x30] + +2: + + # load x19-x30 + ldp x19, x20, [sp, #0x40] + ldp x21, x22, [sp, #0x50] + ldp x23, x24, [sp, #0x60] + ldp x25, x26, [sp, #0x70] + ldp x27, x28, [sp, #0x80] + ldp x29, x30, [sp, #0x90] + + # use third arg as return value after jump + # and as first arg in context function + mov x0, x2 + + # load pc + ldr x4, [sp, #0xa0] + + # restore stack from GP + FPU + add sp, sp, #0xb0 + + ret x4 + .size jump_fcontext,.-jump_fcontext + +# Mark that we don't need executable stack. +.section .note.GNU-stack,"",%progbits diff --git a/src/asm/make_arm64_elf_gas.S b/src/asm/make_arm64_elf_gas.S new file mode 100644 index 0000000..5a6914f --- /dev/null +++ b/src/asm/make_arm64_elf_gas.S @@ -0,0 +1,80 @@ +/******************************************************* + * * + * ------------------------------------------------- * + * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | * + * ------------------------------------------------- * + * | 0x0 | 0x4 | 0x8 | 0xc | 0x10| 0x14| 0x18| 0x1c| * + * ------------------------------------------------- * + * | d8 | d9 | d10 | d11 | * + * ------------------------------------------------- * + * ------------------------------------------------- * + * | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | * + * ------------------------------------------------- * + * | 0x20| 0x24| 0x28| 0x2c| 0x30| 0x34| 0x38| 0x3c| * + * ------------------------------------------------- * + * | d12 | d13 | d14 | d15 | * + * ------------------------------------------------- * + * ------------------------------------------------- * + * | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | * + * ------------------------------------------------- * + * | 0x40| 0x44| 0x48| 0x4c| 0x50| 0x54| 0x58| 0x5c| * + * ------------------------------------------------- * + * | x19 | x20 | x21 | x22 | * + * ------------------------------------------------- * + * ------------------------------------------------- * + * | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | * + * ------------------------------------------------- * + * | 0x60| 0x64| 0x68| 0x6c| 0x70| 0x74| 0x78| 0x7c| * + * ------------------------------------------------- * + * | x23 | x24 | x25 | x26 | * + * ------------------------------------------------- * + * ------------------------------------------------- * + * | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | * + * ------------------------------------------------- * + * | 0x80| 0x84| 0x88| 0x8c| 0x90| 0x94| 0x98| 0x9c| * + * ------------------------------------------------- * + * | x27 | x28 | FP | LR | * + * ------------------------------------------------- * + * ------------------------------------------------- * + * | 40 | 41 | 42 | 43 | | | * + * ------------------------------------------------- * + * | 0xa0| 0xa4| 0xa8| 0xac| | | * + * ------------------------------------------------- * + * | PC | align | | | * + * ------------------------------------------------- * + * * + *******************************************************/ + + .cpu generic+fp+simd + .text + .align 2 + .global make_fcontext + .type make_fcontext, %function +make_fcontext: + # shift address in x0 (allocated stack) to lower 16 byte boundary + and x0, x0, ~0xF + + # reserve space for context-data on context-stack + sub x0, x0, #0xb0 + + # third arg of make_fcontext() == address of context-function + # store address as a PC to jump in + str x2, [x0, #0xa0] + + # save address of finish as return-address for context-function + # will be entered after context-function returns (LR register) + adr x1, finish + str x1, [x0, #0x98] + + ret x30 // return pointer to context-data (x0) + +finish: + # exit code is zero + mov x0, #0 + # exit application + bl _exit + + .size make_fcontext,.-make_fcontext + +# Mark that we don't need executable stack. +.section .note.GNU-stack,"",%progbits

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Friend class with namespace gives compiler error for C6000 TI
by Alin Popa 25 Feb '15

25 Feb '15

Hi, I compile my project with boost header only files, the compiler is C6000 Texas Instruments. The compile errors occurs for example in "boost/algorithm/string/find_iterator.hpp" I have extracted the cause of the problem in the next example code: namespace boost { namespace iterators { class iterator_core_access { public: iterator_core_access(){} ~iterator_core_access(){} }; } using iterators::iterator_core_access; } class testFriend { private: // don't work, compiler error: error: namespace "boost" has no actual member "iterator_core_access" friend class ::boost::iterator_core_access; // here is the problem // it works, compiles ok, this was my cure //friend class ::boost::iterators::iterator_core_access; }; int main () { // it works ::boost::iterator_core_access a; return 0; } Do you guys know what is the reason of this ? With msvc and g++ works fine. Thanks and best regards, Alin

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[build] check __aarch64__ Aarch64
by Oliver Kowalke 24 Feb '15

24 Feb '15

Hi, I've added an pull request for jam.h (build/engine) to set os.platform correctly to 'ARM' on Aarch64 architecture. This is required in order to build boost.context correctly on the64bit ARM platform. thx, Oliver

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Any online C++ compiler with Boost version to select?
by Boris Schäling 23 Feb '15

23 Feb '15

Does anyone know of an online C++ compiler which does not only come with Boost but allows you to select the Boost version? While http://coliru.stacked-crooked.com/ comes with Boost 1.57.0, http://ideone.com/ and http://cpp.sh/ with 1.55.0 and http://codepad.org/ with 1.34.1 (really!), I can't even tell whether these websites support Boost explicitly or whether it's more of an accident that I can include Boost headers. :) http://isocpp.org/blog/2013/01/online-c-compilers also mentions http://liveworkspace.org/ and http://gcc.godbolt.org/. But I can't open these websites (not sure whether they are temporarily broken or gone for good?). Boris

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[config] test macro for std::index_sequence<>?
by Oliver Kowalke 23 Feb '15

23 Feb '15

Hi, I can not find an macro (BOOST_NO_CXX11_...) for testing the absence of std::index_sequence<> - may I have overlooked it? so long, Oliver

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Re: [boost] [gsoc15] Attn: We need 2015 mentors and project ideas for Boost!
by Antonio Colino 22 Feb '15

22 Feb '15

Here is a random thought for a project idea. Agner fog created a vectorization lib for the sse and avx instruction sets as part of a project called vector class. Intel created the equivalent opencl kernels as part of a project that is called ispc ( Intel simd program compiler ). Research both and submit a single vector lib that auto vectorizes avx, sse both gpu and cpu overloading the std::vector class operators.Just a random thought. Intel SPMD Program Compiler)

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[mpl] Fix to Ticket #11001
by Bruno Dutra 22 Feb '15

22 Feb '15

I just finished a pull request <https://github.com/boostorg/mpl/pull/14> with a fix for Ticket #11001 <https://svn.boost.org/trac/boost/ticket/11001>, which, by the way, I reported myself, so I'm quite confident it's fixed. Could one of the maintainers kindly review it? Oh and it is worth it to mention that I also included a new test case to ensure the fix is working. Kind regards, *Bruno C. O. Dutra*

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GSoC: Enhanced vector and deque containers
by Benedek Thaler 22 Feb '15

22 Feb '15

Hi, I'm looking at the "Enhanced vector and deque containers"[0] item of the GSoC projects. I have to following interface idea: boost::devector: Like std::vector, but the first call to push_back inserts the element to the middle of the buffer. Likewise, reserve puts the contents to the middle of the new buffer (if any). This allows a cheap push_front, pop_front, push_back, pop_back. boost::deque: Like std:deque, but segment size can be specified in the constructor. To make buffer operations easier, a `segment_end` would be provided: iterator segment_end(iterator begin) Which returns the end of the largest consecutive range starting at `begin`. I'm also thinking about the following twist: Assuming this layout: [a,b,c,d] [e,f,g,_] Brackets denote segments, letters are elements, underscore is empty space. Here, inserting `x` after `d` normally results several moves and this layout: [a,b,c,d] [x,e,f,g] But instead, we could allocate a new segment: [a,b,c,d] [_,x,_,_] [e,f,g,_] To make the insertion cheaper. This behavior is similar to a segmented list, i.e: std::list<boost::devector<T>> Are these similar to the "extra functionality" mentioned in the docs you were thinking about? Thanks, Benedek [0]: https://svn.boost.org/trac/boost/wiki/SoC2015#a5.Enhancedvectoranddequecont…

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Enquiry about gsoc project Enhanced vector and deque containers
by Jasdeep Singh 21 Feb '15

21 Feb '15

I had a few doubts regarding this project and was wondering if someone could help me out.It would be much appreciated.

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[MultiIndex] Memory consumption of ordered indices
by Olaf van der Spek 21 Feb '15

21 Feb '15

Hi, What's the memory consumption of ordered indices? Is it implemented as a linked list, so two pointers per element? In that case for a write-only data structure an external ptr vector would make more sense wouldn't it? -- Olaf

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