I've had delivery turned off for the last month, so this probably won't thread correctly... This is similar to the issue of modelling logic in hardware description languages. Verilog, for example, has a 4-value type which is pretty much identical to tribool, except that it adds an additional 'tristate' value. Some objects default unknown, some tristate. VHDL has a more comprehensive (user-defined) 9-value logic type, which defaults to uninitialised. Logic on this type is fairly complex, but it includes both the obvious uninit and unknown semantics, and objects default to uninitialised. Having something like this as a tribool extension would be *very* useful. At a minimum, a usable type should have 4 values (U,0,1,X for uninit,0,1,unknown) and should default to U. Maybe I'll get around to this one day... :) Paul