On 1 Jul 2014 at 13:34, Adam Romanek wrote:
See above for my private conversation with Andrey Semashev on this topic (he does not follow the boost-users mailing list).
Andrey says that the "reference counting example" from Boost.Atomic docs is broken. What do you think about this?
I wouldn't be surprised. Few have access to non-Intel hardware for testing, and all Intel CPUs always acquire loads and always release stores. That makes use of atomics with anything but memory_order_seq_cst superfluous on Intel at the CPU level. Additionally, modern CPUs do very well with memory_order_seq_cst across the board, even an ARM Cortex A15. If I ever find myself tempted to not use memory_order_seq_cst before benchmarking I usually slap myself hard. The only real problem with its use is that compilers basically turn off optimisation around them, so you'd rather not have them in tight loops if possible. The ONLY thing which might penalise this approach in the future is memory transactions - I can see memory_order_seq_cst would have to abort more frequently than other orderings. But until such hardware capability is here, I really wouldn't worry. If you see problem code not using memory_order_seq_cst, change it to that and bypass the hassle. Niall -- ned Productions Limited Consulting http://www.nedproductions.biz/ http://ie.linkedin.com/in/nialldouglas/